The present invention relates to a routing method for use in automatically designing the wiring of printed wiring boards, large scale integrated circuit (LSI) chips or the like.
An example of a prior art routing method used for an automatic wiring design in computer-aided design (CAD) systems or the like is disclosed in the specification of the U.S. patent application Ser. No. 835,238 filed Mar. 3, 1986, now U.S. Pat. No. 4,752,887. The method described in the specification uses fixed obstacle data input at the time of initialization as wiring obstacle data for use in the search for a wiring path. According to this method, only total wiring prohibition data are set for the grid points of the wiring path positions discovered upon completion of the wiring of each segment. The data indicate the total impossibility of the wiring to proceed to such grid points.
Therefore, in designing the wiring of a printed wiring board or an LSI having two layers of wiring grids, even if some other wiring arrangement runs on one layer, a wiring arrangement can be routed on the other layer with complete freedom. As a result, there is the major disadvantage that the circuit may be caused to commit an error by a high level of crosstalk generated by the parallel running of wiring arrangements on the upper and lower layers, one having the same horizontal coordinates as the other.
An object of the present invention, therefore, is to provide a routing method free from the above-mentioned disadvantage.